1. Field of the Invention
The present invention relates, for example, to a semiconductor circuit used as a buffer circuit having the function of compensating a power source fluctuation and used for the amplification of a clock signal of a dynamic memory.
2. Description of the Prior Art
One of the conventional buffer circuits which amplifies an input clock signal .phi..sub.0 (hereinafter clock .phi..sub.0) (conversion of impedance) and supplies an output clock signal .phi..sub.1 (hereinafter clock .phi..sub.1) is constituted of MOS transistors Q1 through Q12 (Q9 is a MOS capacitor), as shown in FIG. 1. The input stage of the buffer circuit is a delay circuit constituted of the transistor Q1 through Q4. During the standby period the delay circuit holds the voltage of the node N2 which connects the source of transistor Q3 with the drain of transistor Q4 at a high level by using the input clock .phi..sub.0 and the inverted input clock signal .phi..sub.0 (hereinafter clock .phi..sub.0). The clock .phi..sub.0 is at a high level during the active period and is at a low level during the standby period. The clock .phi..sub.0, because of the inverted polarity, is at a low level during the active period and is at a high level during the standby period. These clocks turn off the transistor Q1, turn on the transistors Q2 and Q3, hold the node N1 at a low level, which node N1 connects the source of the transistor Q1 with the drain of the transistor Q2 and the gate of the transistor Q4, turn off the transistor Q4, and charge the node N2 to the voltage of (Vcc-Vth) through the transistor Q3 during the standby period. The Vcc is the voltage of the high voltage side in the power source and is usually 5 volts, which is the standard value allowing for an error of .+-.10%. The Vth is a threshold value of the transistor. Since the gate of the transistor Q5 is connected to the power source Vcc, when the node N2 is charged to the voltage of (Vcc-Vth), the node N3 is charged to the same voltage. The node N3, which connects the transistor Q5 with the gate of transistor Q6, is the gate terminal of the transistor Q6 in the bootstrap circuit, including the transistors Q6 and Q7. By charging the node N3 to a high level during the standby period, the charged voltage of the node N3 drives, at a high speed, the output stage, including the transistor Q8 through Q12, at the next active period. Since the clock .phi..sub.0 is at the high level during the standby period, the transistor Q7 turns on, the node N4 which connects the source of transistor Q6 with the drain of the transistor Q7 and MOS capacitor Q9 and the gate of transistor Q11, turns to a low level, the transistors Q8 and Q11 turn off, the transistors Q10 and Q12 turn on, and the output clock .phi..sub.1 is at the low level, which is equal to the low level side of the power source Vss (usually ground voltage).
Entering in the active period the input clock .phi..sub.0 and .phi..sub.0 are inverted. In FIG. 2, waveforms of the operation are shown during the active period, and this example shows the case of the constant Vcc which is equal to 4.5 volts. Since, in this example, the voltage of the node N2 is equal to the voltage of the node N3 and the voltages of these nodes are (4.5 volts-Vth), when the clock .phi..sub.0 is changed from Vcc to Vss and the clock .phi..sub.0 is raised from Vss to Vcc, the voltage of the node 3 rises more than (Vcc+Vth) and the voltage to the node N4 is charged to the voltage of .phi..sub.0, which is equal to Vcc, by the bootstrap effect, which is caused by the effects of the capacity between the gate and the drain of the transistor Q6 and between the gate and the source of the transistor Q6.
This results in the transistors Q8 and Q11 being turned on. At the same time, since the transistor Q1 turns on, the transistor Q2 turns off; the node N1 is charged up and the transistor Q4 turns on; then the voltage of the node N2 begins the decrease. Accordingly, the electric charges on the node N3 are deprived through the transistor Q5 and the voltage of the nodes N3 and N2 decreases to the voltage of Vss. When the voltage of the node N2 falls to a voltage of (Vss+Vth) the transistors Q10 and Q12 turn off and the voltage of the node N5 rises up to the voltage of Vcc. At this time, since the voltage of the node N4 is raised to more than (Vcc+Vth) through the capacitor Q9, the output clock .phi..sub.1 rises to the maximum voltage level Vcc.
The above-mentioned operation is carried out when no fluctuation of the power source occurs, while, as shown in FIG. 3, if the fluctuation of the power source occurs during the standby period, the output clock .phi..sub.1 is delayed, and delay of the output clock .phi..sub.1 creates a defect. In FIG. 3, the example is shown in which the voltage of the Vcc decreases from 5.5 volts (Vcc(U)) to 4.5 volts (Vcc(L)) during the standby period. The above-mentioned fluctuation occurs or the fluctuation of other devices connected to the power source occur because the electrical constitution of the constant voltage power supply is simplified, thereby causing a decrease in the production cost. During the standby period, the voltage of the clock .phi..sub.0 is low, the voltage of the clock .phi..sub.0 is high and the voltage of Vcc is 5.5 volts, causing both the nodes N2 and N3 to be charged up to the voltage of (5.5 volts-Vth). Further, if the voltage of Vcc decreases to the voltage of 4.5 volt during the standby period, the voltages of the nodes N2 and N3 (5.5 volts-Vth) do not change because there is no discharge path. The reason there is no discharge path is that the transistor Q4 holds off, and the Q.sub.3 goes to off state because the gate voltage of Q.sub.3 goes to 4.5 volts from 5.5 volts with the power source fluctuation. When the holding of the voltages of the nodes N2 and N3 is effected, the rising of the clock .phi..sub.1 is delayed. In order to raise the clock .phi..sub.1, it is necessary that the transistors Q10 and Q12 are turned off; on the other hand it takes time for the voltage of the node N2 to fall to the low level at which the transistors Q10 and Q12 are turned off, because the voltage of the node N2 is 1 volt higher than the voltage of (4.5 volts-Vth) in FIG. 2. During the delay time when the voltage is falling from the node N2, the delay of the rising of the clock .phi..sub.1 occurs. In FIG. 3 the waveforms indicated by lines N2', N3', N5' and .phi..sub.1 ' show the passages of the voltage changes at the nodes N2, N3 and N5 and the voltage of the clock .phi..sub.1 without a power source fluctuation, as compared with the broken lines N2, N3, N5 and .phi..sub.1, which show the passages of the voltage changes at the same portions when the fluctuation occurs in the power supply.
The present invention is proposed in order to minimize the above-mentioned problems.